Today, mobile electronic devices have become an important part of our lives and culture. The adoption of touch technology on tablets and smartphones allows us to interact more with these devices. It constitutes a complete electrostatic discharge (ESD) hazardous environment, that is, the electrostatic discharge generated by the human skin on the equipment.

For example, when using consumer electronic devices, ESD can occur between the user's finger and the tablet USB or HDMI port, which can cause irreversible damage to the tablet, such as peak standby current or permanent system failure.

1. Comparison between system-level ESD protection and device-level ESD protection

ESD damage to ics can occur at any time, from assembly to board level welding to end-user human-machine interaction. Esd-related damage dates back to the earliest days of semiconductor development, but it only became a widespread problem after microchips and thin-gate oxide FETs were applied to highly integrated ics in the 1970s.

All ics have some embedded device-level ESD structure to protect the IC from ESD events during the manufacturing phase.

These events can be simulated by three different device-level models: the human body model (HBM), the machine model (MM), and the charged device model (CDM).

HBM is used to simulate ESD events caused by user operation, MM is used to simulate ESD events caused by automatic operation, and CDM is used to simulate ESD events caused by product charging/discharging. These models are used for testing in manufacturing environments. In this environment, assembly, final testing, and board level welding are performed in a controlled ESD environment, thereby reducing ESD stress on exposed devices. In a manufacturing environment, ics are generally only able to withstand ESD shocks of 2-kV HBM, and the recently introduced electrostatic regulations for small devices are as low as 500V.

While device-level models are generally adequate in a factory-controlled ESD environment, they fall far short in system-level testing. In the end-user environment, the ESD shock intensity of voltage and current is much higher.

Therefore, industrial environments use another method for system-level ESD testing, which is defined by the IEC 61000-4-2 standard. The purpose of HBM, MM and CDM testing at the device level is to ensure that the IC is not damaged during the manufacturing process. The system-level tests specified by IEC 61000-4-2 are used to simulate real-world end-user ESD events.

The IEC defines two types of system-level tests: contact discharge and non-contact discharge. When using the contact discharge method, the test simulator electrode remains in contact with the device under test (DUT). In non-contact discharge, the charged electrode of the simulator is close to the DUT, and the spark generated between it and the DUT causes the discharge.

Table 1 lists the range of test levels for each method specified in the IEC 61000-4-2 standard. Note that the discharge strength is not the same for each test level of the two methods. We typically test stress levels step by step above level 4 (the highest official nominal level for each method) until the point of failure occurs.

Table 1: Test levels for contact discharge and non-contact discharge methods

There are some clear differences between the device-level model and the system-level model, which are listed in Table 2.

Table 2: Device pole model compared with IEC system level model

The last three parameters in Table 2 (current, rise time, and number of shocks) require special attention:

a, the current difference is critical to whether ESD sensitive devices can withstand an ESD event. Since strong currents can cause junction damage and gate oxidation damage, 8-kV HBM protection chips (peak current 5.33A) can be damaged by 2-kV IEC model shocks (peak current 7.5A). It is therefore extremely important that system designers do not confuse HBM ratings with IEC model ratings.

B. Another difference exists in the voltage peak rise time. The specified rise time of HBM is 25ns. The IEC model pulse rise time is less than 1ns, which consumes most of the energy in the first 3ns. If a HBM-rated device requires 25ns to respond, the device is damaged before its protection circuit is activated.

C. The two models used different electric shocks during the test. HBM requires only one positive shock and one negative shock to be tested, whereas the IEC model requires 10 positive shocks and 10 negative shocks. It may be the case that the device can withstand the first shock, but because the damage from the initial shock is still there, it will fail after a subsequent shock. Figure 1 shows examples of ESD waveforms for CDM, HBM, and IEC models. It is obvious that the IEC model pulse carries more energy than the pulse of all device-level models.

Figure 1: ESD waveforms for device poles and IEC models

2. How does TVS protect the system from ESD events

Unlike ESD protection integrated structures, the IEC 61000-4-2 standard defines models that typically use discrete independent transient voltage suppression diodes, also known as transient voltage suppressors (TVS). Stand-alone TVS cost less than ESD protection integrated in a power management or microcontroller unit and can be placed close to the system I/O connector, as shown in Figure 2.

Figure 2: TVS layout of the system pole

There are two types of TVS: two-way and one-way (see Figure 3). The TI TPD1E10B06 is an example of a two-way TVS that can be placed on a universal data line for system-level ESD protection.

Figure 3: Two-way and one-way TVS

In normal operation, both two-way and one-way TVS are open for one and grounded in the event of an ESD event. In the case of two-way TVS, as long as both D1 and D2 do not enter their breakdown area, the I/O line voltage signal will swing up and down the ground voltage.

When an ESD shock (positive or negative) hits the I/O line, one diode becomes positively biased and the other breaks down, creating a path along which ESD energy is immediately grounded. In the case of unidirectional TVS, as long as neither D2 nor Z1 enter their breakdown zone, the voltage signal will swing above the ground voltage.

When a positive ESD shock hits the I/O line, D1 becomes forward biased, and Z1 enters the breakdown zone before D2. A grounding path is formed through D1 and Z1 to dissipate ESD energy.

When a negative ESD event occurs, D2 becomes positively biased and ESD energy is dissipated through the D2 grounding path. Because D1 and D2 sizes can be smaller and have less parasitic capacitance, unidirectional diodes can be used in many high-speed applications; The D1 and D2 can "hide" the larger Zener diode Z1 (the reason for the large size is to handle more current in the breakdown area).

3. Key device parameters of system-level ESD protection

Figure 4 shows a comparison of the current and voltage characteristics of TVS diodes. Although TVS is a simple structure, several important parameters still need to be paid attention to during the design process of system-level ESD protection.

These parameters include breakdown voltage VBR, dynamic resistance RDYN, clamp voltage VCL, and capacitance.

Figure 4: Relationship between current and voltage of TVS secondary tube

3.1. Breakdown voltage VBR

The first step in choosing the right TVS is to study the breakdown voltage (VBR).

For example, if the maximum operating voltage of the protected I/O line, VRWM, is 5V, the TVS should not enter its breakdown zone until that maximum voltage is reached. Usually, TVS product manuals include VRWM for specific leakage currents, which makes it easier to choose the right TVS. Otherwise, we can choose a TVS with a VBR (min) greater than the VRWM of the protected I/O line by a few volts.

3.2. Dynamic resistance

ESD is a speed event, which is a matter of nanoseconds. In such a short period of time, the TVS conduction ground path will not be immediately established, and there is a certain resistance in the path. This resistance is called dynamic resistance (RDYN) and is shown in Figure 5.

Figure 5: ESD current discharge path

Ideally, RDYN should be zero so that the I/O line voltage is as close to VBR as possible; But that's not going to happen.

The latest industry standard value for RDYN is 1 Ω or less. RDYN can be obtained by using transmission line pulse measurement technology. With this technique, the voltage is released through the TVS and the corresponding current is measured. After obtaining many data points of different voltages, an IV curve like that shown in Figure 6 can be drawn, and the slash line is RDYN. Figure 6 shows the RDYN of TPD1E10B06, with a typical value of ~ 0.3Ω.

Figure 6: IV characteristics of TPD1E10B06

3.3 Clamp voltage

Since ESD is an extremely fast transient event, the voltage of the I/O line cannot be clamped immediately. As shown in Figure 7, thousands of volts are clamped to tens of volts according to IEC 61000-4-2.

Figure 7: ESD event clamp for 8Kv contact discharge

As shown in equation 1, the smaller the RDYN, the better the clamping performance:

Where IPP is the peak pulse current during an ESD event, and Iparasitic is the line parasitic inductance from the connector grounded through TVS.

Think of the area below the clamp voltage waveform as energy. The better the clamping performance, the less likely the protected ESD sensitive device will be damaged in an ESD event. Due to the small clamping voltage, some TVS can withstand the 8kV contact discharge of the IEC model, but the "protected" device is damaged.

capacitance

In normal operation, TVS is an open circuit and has a parasitic capacitance shunt ground. Designers should take this capacitance into account in the signal chain bandwidth budget.

conclusion

As the IC process technology node becomes smaller and smaller, it is also increasingly vulnerable to ESD damage, both in the manufacturing process and in the end-user environment. Device-level ESD protection is not sufficient to protect ics at the system level. We should use standalone TVS in system level design. When choosing a TVS, designers should pay attention to some important parameters, such as: VBR, RDYN, VCL and capacitance.